The present invention relates to a semiconductor device, and a technology effective when applied to, for example, a semiconductor device including a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor).
There has been described in Japanese Unexamined Patent Application Publication No. 2007-266218 (Patent Document 1), a manufacturing technology of a semiconductor device using a metal plate frame in which regions for supporting metal plates by suspension portions are arranged in plural in a matrix form.
There has been described in Japanese Unexamined Patent Application Publication No. 2010-67755 (Patent Document 2), a manufacturing technology of a semiconductor device in which each individual metal plate is mounted over a semiconductor chip.
There has been described in Japanese Unexamined Patent Application Publication No. 2002-83918 (Patent Document 3), a technology in which semiconductor chip mounting portions are assembled in plural in a matrix form to configure a unit frame assembly, and the unit frame assembly is provided to a lead frame base. At this time, a support bar obtained by removing the back side of each unit frame and forming thinner at least a portion to be cut, a tie bar formed thinner than the thickness of the lead frame base, and a boundary portion formed thinner than the thickness of the lead frame base are formed in a lead frame.